The semiconductor industry continuously progresses toward the use of semiconductor die assemblies and packages exhibiting ever-smaller footprints (i.e., length and width), as well as heights. Such progress frequently entails the use of so-called “3-D” assemblies and packages, wherein a number of semiconductor dice are assembled in a stack. Initially, such die stacks, for example, stacks of memory dice in the form of dynamic random access memory (DRAM) included only a single type of die. However, more recently it has been recognized as desirable to incorporate a logic die with a stack of DRAM dice, such an assembly and package sometimes being referred to as a “hybrid memory cube.”
While such assemblies and packages of DRAM with logic are, in theory, an improvement in the state of the art, practical implementation of such assemblies and packages has been difficult due to the relatively high heat output of the logic die, which is transferred to the adjacent DRAM in the assembly by conduction through the semiconductor material of the adjacent dice and, perhaps as significantly, through so-called “through silicon vias,” or “TSVs,” comprising conductive vias in the DRAM dice and conductive pillars extending between the adjacent DRAM die and the logic die as well as between the adjacent DRAM die and other DRAM dice in the stack which may comprise, for example, four, eight, twelve or some other number of DRAM dice.
FIG. 1 is a schematic cross-sectional view of a potential configuration of a 3-D package 100 comprising a logic die 102 and four DRAM dice 104a-104d stacked thereon. The 3-D package 100 as illustrated herein and described below is by way of example only, has not been produced by the assignee of the present disclosure and is not admitted to be prior art. As shown, all dice but the top DRAM die 104d have TSVs 106 extending therethrough. The TSVs 106 are, in turn, mutually connected by external connection elements 108 for signal, power and ground/bias connections between logic die 102 and the various DRAM dice 104a-104d. In the illustrated package 100, external connection elements 108 may comprise copper pillars 110 with solder caps 112.
The logic die 102 is mounted to an interposer 114, which may comprise silicon. Interposer 114 includes conductive traces 116 on a surface thereof facing logic die 102, and logic die 102 is operably coupled to distal ends of conductive traces 116 with external connection elements 118, which may comprise copper pillars 110 with solder caps 112. Conductive traces 116 extend to copper posts 120 extending through interposer 114 and protruding therefrom on a surface opposing that on which conductive traces 116 are located, copper posts 120 being capped with solder 122 for use in connecting the interposer 114 to higher-level packaging, for example a motherboard or other circuit board.
Heat spreader 124, which may comprise any suitable material, such as a metal or metal alloy, extends over DRAM dice 104a-104d and logic die 102 in operable heat-transferring contact with uppermost DRAM die 104d and contacts interposer 114 along a lateral periphery thereof. A thermal interface material (TIM) (not shown) may, optionally, be interposed between the DRAM die 104d and an inner surface of the heat spreader. Within heat spreader 124, DRAM dice 104a-104d and logic die 102 are encapsulated with a dielectric molding compound 126. Volumes between the various DRAM dice 104a-104d and logic die 102 and surrounding external connection elements 108 may, prior to encapsulation, be filled with a dielectric capillary underfill, a non-conductive paste or a non-conductive film 130.
Such a package as described above may exhibit operational temperatures in excess of specification for both logic die 102 and DRAM dice 104a-104d. More specifically, Tmax for logic die 102 should be maintained under about 105° C., while Tmax for DRAM dice 104a-104d should be maintained under about 95° C. However, with 3-D package 100 configured as described above, logic die 102 may exhibit an operating temperature of, for example, in excess of 127° C., while DRAM die 104a may exhibit an operating temperature of about 109° C., both such temperatures being well in excess of specification.
Various approaches have been proposed to mitigate the excessive heat generated by a logic die, including the use of complex heat sink or spreader structures, as well as active package cooling. However, it would be desirable to implement an effective, passive thermal isolation architecture for any die assembly or package requiring control of excessive heat generated by a semiconductor die of such assembly or package.